parity check

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  • noun

Synonyms for parity check

a system of checking for errors in computer functioning

References in periodicals archive ?
By cyclically shifting the [H (*).sub.0] within the sections q - 2 times, we can obtain the whole parity check matrix H.
For the data used, we have included parity check, modulation and channel types and number of iteration from published works wherever given.
Here H is called the parity check matrix (PCM) and the illustrated form is given as given in equation 5
where H is a parity check matrix for some Hamming code, and the quotient is a complete graph;
It is difficult to apply (3) to BCH codes directly because the parity check matrix is not sparse.
RSCC of rate L/N is applied on each column of L bits, from which N-L parity check bits are obtained.
The parity check matrix of all six code classes consists of 24 columns and (1-R) *24 rows, with each entry describing a z-by-z sub-matrix which is either a permuted identity matrix or a zero matrix.
The randomly chosen synchronization positions have low influence on the recognition of code length, but the recognition of key parameter [n.sub.a] (the minimal length of the rows of matrix [R.sub.l] so that [R.sub.l] includes dependent columns; see [7] for details) and parity check vectors are not correct.
Table 1 depicts that among all the mechanisms DMR has the highest overhead, T-MR has moderate and parity check has least hardware overhead.
The corresponding neutrosophic parity check matrix is given as follows,
It supports VersaFEC and Low Density Parity Check (LDPC) forward error correction, DoubleTalk Carrier-in-Carrier[R] bandwidth compression and the IP Packet Processor with advanced QoS and compression.
Advanced beamforming, Low-Density Parity Check (LDPC) code and SpaceTime Block Code (STBC) support for better coverage and more reliable connectivity.
Gallager, "Low-density parity check codes," IRE Transactions on Information Theory, vol.
The data symbols [X.sub.d] are encoded using the LDPC parity check matrix for FEC at the receiver.
A critical piece of intelligence integrated into the new 28nm SoC is the LSI TrueStore RC5100, a 28nm read channel featuring third-generation LSI low-density parity check (LDPC) iterative decoding architecture.