Therefore, the optimal solution should be to use dynamic remapping for cache attacks against L2 cache and LLC, and use cache cleansing for cache attacks against L1 cache
This architecture also introduced a L1 cache
associated with each streaming multiprocessor that offers the possibility to be managed by the programmer or automatically, by the hardware.
This work extends the experiment for different technologies not keeping limited to different cache bus width and L1 cache
Configuration: One central server: Fujitsu Siemens Computers PRIMEPOWER 900, 8-way SMP, SPARC64 V, 1.35 GHz, 256 KB L1 cache
, 2 MB L2 cache, 32GB main memory
It includes 128 KB of L1 cache
and support for 512 KB to 8 MB of L2 cache.
In TPCM, we constrain the procedure addresses modulo the L1 cache
Since prefix databases are fairly large and the L1 cache
is quite small, we (pessimistically) chose to ignore the effects of L1 caching.
provides information with effectively no pipeline stalls but is relatively small, while L2 cache has much more storage space but also higher latency (which means lost efficiency as the CPU cores wait for data to arrive from L2 cache).
The units also feature 64 KB L1 cache
, 1 MB L2 cache, three Ethernet interfaces up to Gb speed, and two 64-bit PMCs on independent PCI buses.
They offer 64 K of unified instruction and data L1 cache
and Socket 7 motherboard compatibility for inexpensive deployment.
First, the additional interthread conflict misses in the direct-mapped L1 cache
are almost entirely covered by the 4-way set associative L2 cache, as shown in Figure 8.
System Processor Intel[R] Core[TM]2 Duo L7400 (LV), 1.5 GHz, 667 MHz FSB, 4 MB L2 cache 479-pin [mu]FCBGA package, 2x 32KB L1 cache
and 4 MB L2 cache The processor is passive cooled with a fanless heatsink.