SaDPT represents a pivotal advancement beyond the charge trap flash
(CTF) technology that Samsung developed for NAND flash last year when it introduced a new material (silicon nitride) and a new structural configuration.
For example, the latest flash-memory processes feature advanced technologies, such as charge trap flash
(CTF) and multi-level cell (MLC) designs, as well as ever-smaller feature sizes.
Another highly significant paper being presented by Samsung at IEDM 2006 focuses on the development of NAND flash memory based on charge trap flash
(CTF) technology, which Dr.
The new 32 Gigabit (Gb) NAND flash device is the first memory to incorporate a Charge Trap Flash (CTF) architecture, a revolutionary new approach to further increase manufacturing efficiency while greatly improving performance.
Floating Gate) Charge Trap Flash Floating Gate Development 2006 (Samsung) 1989 (Toshiba) Structure Single Gate Dual Gate (Control Gate) (Control/ Floating Gate) Fabrication Simple Complex (Cell height) (one fifth of the floating gate) Control gate Height One fifth of the floating gate - Material Metal (TaN) Poly Silicon Storage level Height One tenth of a floating gate - Material Non-conduct (SiN) Conduct (poly-Si) Inter-Cell Noise Level No interference Interference at floating gate Scalability Greater than 20nm-level, Greater than 50nm- up to 256Gb level, up to 16Gb Process Steps Reduces process step by 20 percent - Cell Size Reduces cell size by 28 percent -