This technique states that we should replace the cache line
that has not been accessed for the longest period.
The authors evaluate a hybrid scheme which combines the three techniques and propose using transmission lines only to access the central banks where the cache lines
are concentrated due to block migration.
Since instruction accesses are fairly sequential, it is usually helpful to bring in more than one cache line
by a software prefetch.
In a direct-mapped cache, the relationship between the memory address and the cache line
number is simply
The cache lines
in a multiway associative cache are divided among a number of sets, each containing the same number of lines.
During this stage, the instruction fetcher retrieves two instructions at a time from the instruction cache (regardless of alignment), unless the address points to the last word of a cache line
, in which case only a single word is returned.
The number of forward and backward pointers is proportional to the number of cache lines
in the machine, which is much smaller than the number of memory lines.
The entry labeled "Remote Software" reports the cost of a miss to a cache line
under software directory control (the Alewife cache coherence protocol, known as LimitLESS [Chaiken et al.
The cache considered is an 8KB two-way set-associative cache with 128 cache sets and four data elements per cache line
The processor also supports cache line
locking and prefetching for improved performance.
When a READ is done to memory of a single word, the entire cache line
is fetched into the cache.
Since the MSHR already prevents the result of a miss fetch from entering the first-level cache if a load instruction is squashed before the data returns, we simply have to solve the problem of invalidating a cache line
if an informing load miss completes before the load is ultimately squashed.
Data locality occurs whenever a cache line
is reused, provided that the line has not been ejected from the cache since it was last used.
On average assuming a cache line
has four words, and on average two words per write are in cache then bus utilization improves by more than two-fold.
Each entry occupies 16 bytes; therefore, a bucket occupies one cache line
(64 bytes) on an Alpha 21164, so we incur at most one data cache miss to search the entire bucket.