Multiple methods are proposed, including locking cache lines
for different VMs , partitioning caches  and separating memory pages according to the mapping relationship with caches .
Flush + Reload utilizes the assembly mnemonic clflush() that enables the cache flush to operate at the granularity of cache lines
. To perform time measurement, this method uses the processor's hardware API, the rdtsc().
In shown table 1 r the processor management with sets of cache as one set is controlled by cache depends upon the size and location of cache lines
Since instruction accesses are fairly sequential, it is usually helpful to bring in more than one cache line
by a software prefetch.
Given a cache line
n of a direct- mapped cache, a set S of program code blocks mapping to n, and an execution trace of program code blocks,
Table IV also displays some cache memory characteristics, namely the associativity of the cache, cache size (in kilobytes), and cache line
size (in bytes).
Sequential prefetch, for example, fetches the cache line
following the current line.
In other words, it means that when a data is not in L1, we need to copy a whole cache line
from L2 or L1 but only a few of the bytes in this cache line
The victim cache is loaded with the victim of a cache miss rather than the missed cache line
A memory line refers to a cache-line-sized block in the memory, while a cache line
refers to the actual cache block to which a memory line is mapped to.
These include: the number of execution units, the number of pipeline stages of the floating-point execution unit, the size of cache, the size of the dispatch buffer, the instruction cache line
size, and others.
For each cache line
in the page, the processor forces the cache-coherence hardware to issue an invalidation for the cache line
These results are echoed also in our pollution results: when a cache line
replaces a line in SPEC'95 that line tends to be reused spatially: on average, 42% of lines are reused only spatially, and an additional 38% are reused both spatially and temporally (Figures 67 and 70).
When a READ is done to memory of a single word, the entire cache line
is fetched into the cache.