In practice, cache coherency
is supported by the vendor up to a certain level of parallelism, say, 128 processors in the Silicon Graphics Origin2000.
Doze mode disables most functional units but maintains data cache coherency
by enabling the bus interface unit and snooping.
The elimination of cache coherency
in the IBM system comes as no surprise, because cache-coherent operations are a known scaling bottleneck.
Maintaining cache coherency
is complicated and adds additional time and overhead to the processor-to-processor communications protocols.
* RAID technology is now well understood, as are most of the standard processes within a RAID controller such as cache coherency
, read and write processes, RAID set rebuilds, volume management, mirroring, and snapshot.
For general computing, we need designs that share memory with guaranteed cache coherency
, and that allow each core to run instruction streams independently of the others.