In this section, we present our shadow dynamic finite state machine (SDFSM) branch prediction
technique for learning/predicting an application's unique branching patterns.
In addition, productivity applications include code which is not especially ordered or predictable, which will necessarily limit gains in the chip's branch prediction
mechanisms, mechanisms that rely on predictable code to increase performance.
For the SPECint95 benchmarks, moving from perfect to realistic branch prediction
shows a performance degradation, because it reduces the number of useful instructions that are ready to issue each cycle.
The most successful application of branch correlation has been in dynamic branch prediction
, where architects have built predictors that remember patterns in the stream of branch executions [McFarling 1993; Pan et al.
The idea of using prediction in computer architecture is not new; it has already found important application in branch prediction
and speculative execution in general.
According to Intel, dynamic execution is composed of three parts: multiple branch prediction
, data flow analysis, and speculative execution, which work together to manipulate data rather than to simply process a list of instructions.
operating system (selectively) disable branch prediction
hardware whenever a
The CPU's 64KB of L1 (32KB instructions, 32KB data) ensure a high hit rate and keep branch prediction
stalls to a minimum.
“The 4th generation Intel[R] Core[TM] i7 and Core[TM] i5 processors deliver a significant performance jump over their predecessors by combining 22nm process technology with numerous core improvements including transactional synchronization extensions (TSX), next generation branch prediction
, more instruction parallelism and more load/store bandwidth,” said Robert Day the VP of Sales and Marketing for LynuxWorks, Inc.
Precise branch prediction
is required to overcome this performance limitation imposed on high performance architecture and is the key to many techniques for enhancing and exploiting Instruction-Level Parallelism (ILP).
Other themes are coherence, applying compilers and debugging support, chip multiprocessor memory hierarchies, runahead and branch prediction
, inconnection networks, and load and store queues.
A dynamic branch prediction
circuit eliminates idle cycles during execution of change-of-flow instructions to accelerate new and existing StarCore programs by an average of 10 percent.
This technique involves the introduction of a branch prediction
mechanism [Smith 1981; Yeh and Patt 1991; 1992; 1993] and a means for allowing the processor to continue executing control-dependent instructions before resolving the branch outcome.