standard cell

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a primary cell used as a standard of electromotive force

References in periodicals archive ?
The lower layers of a ChipX Structured ASIC are filled with structured array cell elements -- also known as a structured array fabric -- including memory, I/O structures, analog macros and physical layer cores.
The ASIC Advantage line of IN-PLUG(R) Controllers features Flyback, Feedback, PFC, Push-Pull and LED controllers.
Our NRE-free ASIC products are designed to expand into a wide range of ASIC and FPGA applications where users consider cost, performance and programmability to be critical.
This brings additional off-the-shelf alternatives to those designers contemplating a Structured ASIC solution.
ASIC product backlog to ChipX and has contracted the completion of the ongoing customer designs to ChipX.
At the leading edge of semiconductor manufacturing, the linkage between process technology and design is increasingly critical, requiring much higher levels of collaboration and customer interaction than have been offered by traditional ASIC vendors.
Increasing Use of Electronics in Automobiles Spurs the Demand for ASIC, ASSP, and FPGAs
When an ASIC takes on more function, you can reduce cost by eliminating one, two or even more separate chips.
Intel pre-approved and qualified AMI's process technology for their products and for Intel-approved ASIC original equipment manufacturer (OEM) buyers.
Embedded arrays add an exciting new option to the products that ChipX customers can use to bring their ASIC to market.
In addition to QPT and CPM enhancements, the automated DesignWare Conversion and automated Gated Clock Conversion features allow designers to use the ASIC RTL as is, without requiring manual changes.
0 Hi Speed OTG compliance certification for CX6200 products, our customers benefit more than ever before from the unique integration benefit that ChipX offers to ASIC designers," said Wouter Suverkropp, Director of Marketing at ChipX.
HARDI is a solid platform for verifying multi-million gate ASIC designs.
Avery is excited to team with ASIC Architect to promote a cohesive design IP and core-to-chip-level verification solution for our customers," said Chilai Huang, president of Avery Design.
Blast Create SA's structure-specific timing optimization allowed us to manage the mapping of the RTL into the programmable logic cells, enabling us to fully leverage the structured ASIC fabric embedded in our Spear(TM) product, achieve timing and minimize area.