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  • noun

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a small adhesive disk of paste

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a small thin crisp cake or cookie

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thin disk of unleavened bread used in a religious service (especially in the celebration of the Eucharist)

References in periodicals archive ?
After the wafers are cleaned, a separator mechanism separates the C[O.
Several of the industry's leading wafer suppliers are already using the new system to more cost-effectively produce defect-free 45nm-generation wafers.
Katsuhiko Miki, General Manager of the SEH Technology and Development Division, said, "Providing defect-free wafers to our customers requires greater quality control with every new chip generation, both to develop more advanced wafer manufacturing processes and to ship superior quality final products.
Tony Di Napoli, President and CEO of NexTech commented: "The deployment of the Pegasus wafer sorting tools in semiconductor fabrication facilities enables the necessary movement of semiconductor wafers in a fully automated and environmentally controlled way.
Wafers are processed two at a time, loaded in a back-to-back wafer holder at the load station.
According to Reid, Ibis believes that these orders substantiate the Company's position that it is the world's silicon wafer manufacturers who are best positioned to meet the increasing demand for production volumes of SOI wafers for the global semiconductor industry.
ADE Corporation (NASDAQ: ADEX) announced today that it has received a multi-million dollar order for several advanced 300mm wafer metrology tools from a leading Asian silicon wafer manufacturer.
Our first lot of wafers for mass production of DRAM using advanced 90 nm process technology started on October 17, 2005," said Shuichi Otsuka, president of Hiroshima Elpida.
Ibis Technology Corporation (Nasdaq NM: IBIS), a leading provider of SIMOX-SOI implantation equipment to the worldwide semiconductor industry, today announced the receipt of an order for an Ibis i2000 oxygen implanter from SUMCO, a leading manufacturer of silicon wafers.
The WaferMate200(TM) workcell is designed to accommodate wafers ranging in size from 100mm to 200mm in diameter, and can be configured with a broad range of options to meet specific handling requirements.
is offering a cost saving alternative of using reclaimed TEOS or thermal oxide dummy wafers for CMP(a) tools retaining ring break-ins and tool startup qualifications after idle time.
In addition to the emergence of SoC flip chip products, the 300 mm wafer format that is fast becoming the industry-standard more than doubles the number of die to be tested on flip chip device wafers and places significant demands and challenges on semiconductor manufacturers' performance testing capabilities.
They can also perform intuitive analysis of defect patterns and trends as they relate to wafers and lots, time periods, lot-routing through the process and performance of a particular process step.
Plasma-enhanced fusion bonding is valuable because the relatively low temperature allows hermetic bonding of microstructure wafers with wafers that already have fully processed circuitry on board.