via

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References in periodicals archive ?
But the primary conclusion from all this is that vias can carry much more current than previously assumed.
Our recommended method is to plug the via with copper or epoxy and have it plated over by the fabricator.
The PCB cross-section of FIGURE 1 shows how conventional conductive filled vias increase the effective interconnect per PCB layer.
Plating vias shut with copper during plating has its own set of challenges.
The return path for a single-ended via is the board PDN, which will consist of stitching vias, decoupling capacitors, and power and ground planes.
Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced that VIA Technologies has adopted RedHawk-SDL and NSPICE-PI as part of its production physical power flow.
ESI's Advanced Packaging Group (APG) product line provides innovative, cost effective via solutions to the high density interconnect (HDI) and advanced packaging markets.
On October 19, 1999, Semiconductor International magazine announced the winners of its "Editor's Choice Best Products Awards for 1999," and Gore's VIA ON CHIP PITCH(TM) substrates were among the select handful of winners.
When using via-in-pad methods, you can spread the vias within the pads and potentially open up a channel to route differential pairs without splitting them.
These vias are embedded in the plane and are located near each ground ball pad.
Our Micro-island Via technology enables fine line geometries and smaller vias, significantly increasing routing density and reducing trace lengths.
1+N+1 = Type II (Layer 1:2 microvias with buried vias in a laminated core)
Although the via sizes are still larger than in an HDI stackup using micro-vias, the blind and buried vias are still small enough to obtain significant route density gains.