In that table we list the Mflops achieved for each version with different numbers of threads.
When operating at a 40-MHz clock rate, each of the DSPs can execute up to 120 MFLOPS and perform a 512-point real FFT in 136 [micro]sec.
Tables, which show measured performance results in Mflops for each routine and choice of parameters.
In 1995, $20,000 distributed computing node microprocessors with peak speeds of 400 to 800 Mflops can provide 20,000 to 40,000 flops/$.
CRAY Y-MP/864 Vector MFLOPS One CPU Program Sisal Fortran KIN16 232 218 RICARD 211 216 CFFT 225 197 BMK11A 46 49 LOOPS 30 39 SIMPLE 20 21 UNSPLIT 104 146 WEATHER 17 17
7 million floating-point operations (mflops) to applications and up to 320 mflops for 3-D graphics processing simultaneously in a shared memory architecture.
Based upon a 6700-class digital signal processor from Texas Instruments, it is capable of 900 MFLOPS (million floating-point operations per second) performance at a Single Event Upset (SEU) rate of 1E-4 unrecoverable errors/day using only 5-7 Watts of power.
The utilization of processors only drops from 82 Mflops to 69 Mfiops when the number of processors increases from 7 to 31.
Compared to the previous-generation 120MHz SH7261, the new 200MHz SH7263 microcontrollers deliver about 70 percent more speed, achieving 480 MIPS (million instructions per second) and 400 MFLOPS (mega floating-point number operations per second) performance.
Starting at 319 MFLOPS per dollar, the SHARC family makes floating-point processing economical for more applications.
Table II contains the performance data from Table I converted to mflops and the mean performance measures as expressed by the arithmetic, geometric, and harmonic means.
Keeping in mind the cost constraint of two minutes of Cray time per frame and the fact that film moves at 24 frames per second, Yaeger noted that for a typical application you would require 65 MFLOPS sustained, assuming 500 operations per pixel-color and a resolution of 2,560 by 2,048.
Through its balanced architecture, the ADSP-TS201 achieves the industry's highest performance density, delivering up to 1800 MFLOPS (million floating point operations per second) per Watt, 85 MFLOPS per dollar and 3600 MFLOPS per square inch of board space.
The new family of TigerSHARC Processors further extends ADI's leading position in performance density, delivering up to 1800 MFLOPS per Watt, 85 MFLOPS per dollar and 3600 MFLOPS per square inch.
The 32 bit DSP will be used for video compression, and has a processing power 198 MFLOPS (32-bit floating-point).