Interference occurs in the cache system when data belonging to one thread is evicted by a cache line
from another thread.
The two-way set-associative caches are nonblocking and support cache line
Conventional design is breaking down because the natural progression to DDR3 causes an architecture incompatibility between the optimal 64-byte burst sizes required for single-channel DDR3 DRAMs and the underlying processor cache line
and primitive data object sizes, such as MPEG, which are normally 32-bytes or less.
To reduce access time, the 26 Series devices support 8-, 16-, 32- and 64-Byte burst mode operation with wrap around, which allows designers to execute code in burst snippets for RAM-less applications or fill cache line
buffers for those applications where the system architecture uses pipelining to maximize bus bandwidth.
The remaining nodes caching the line are joined together in a distributed, doubly linked list, using additional pointers that are associated with each cache line
in a node (which are known as forward and backward pointers).
The processor also supports cache line
locking and prefetching for improved performance.
For example, two functions that use the same cache line
can create contention.