The T630 family is based on a patented, pipelined, single-cycle 8051 core that delivers up to 25 MIPS of CPU bandwidth
while providing high functional density per square millimeter.
The Elf2 also benefits from InHand's award-winning BatterySmart system software suite, with features such as dynamic clock-scaling, reduced power peripheral software drivers, automatic CPU bandwidth
detection and adjustment, and advanced measurement and analysis tools.
The T610 is based on a patented, pipelined, single-cycle 8051 core that delivers up to 25 MIPS of CPU bandwidth
while providing high functional density per square millimeter with on-chip high-performance features such as a highly accurate ADC for analog measurement, voltage regulator and precision internal oscillator ultimately reducing the number of external components and reducing the size and cost of the end-product.
with a similar reduction in CPU bandwidth
A pipelined, single-cycle 8051 core delivers up to 25 MIPS of CPU bandwidth
The XR17C154 enables the transfer of more data bytes in each interrupt service thus reducing CPU bandwidth
Minimizes CPU Bandwidth
Requirements, Increases System Throughput
RDMA was developed in response to the growing demand for increased memory and CPU bandwidth
needed to support high-performance parallel, clustering and grid computing.